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general description the MAX8537/max8539 controllers provide a complete power-management solution for both double-data-rate (ddr) and combiner supplies. the MAX8537 and max8539 are configured for out-of-phase and in-phase ddr power-supply operations, respectively, and gener- ate three outputs: the main memory voltage (v ddq ), the tracking sinking/sourcing termination voltage (v tt ), and the termination reference voltage (v ttr ). the max8538 is configured as a dual out-of-phase controller for point- of-load supplies. each buck controller can source or sink up to 25a of current, while the termination refer- ence can supply up to 15ma output. the MAX8537/max8538/max8539 use constant- frequency voltage-mode architecture with operating frequencies of 200khz to 1.4mhz. an internal high- bandwidth (25mhz) operational amplifier is used as an error amplifier to regulate the output voltage. this allows fast transient response, reducing the number of output capacitors. an all-n-fet design optimizes effi- ciency and cost. the MAX8537/max8538/max8539 have a 1% accurate reference. the second synchro- nous buck controller in the MAX8537/max8539 and the vttr amplifier generate 1/2 v ddq voltage for v tt and v ttr , and track the v ddq within ?%. this family of controllers uses a high-side current-sense architecture for current limiting. ilim pins allow the set- ting of an adjustable, lossless current limit for different combinations of load current and r dson . alternately, more accurate overcurrent limit is achieved by using a sense resistor in series with the high-side fet. overvoltage protection is achieved by latching off the high-side mosfet and latching on the low-side mosfet when the output voltage exceeds 17% of its set output. independent enable, power-good, and soft-start features enhance flexibility. applications ddr memory power supplies notebooks and desknotes servers and storage systems broadband routers xdsl modems and routers power dsp core supplies power combiner in advanced vga cards networking systems rambus memory power supplies features ? MAX8537/max8539: complete ddr supplies ? max8538: dual nontracking controller ? out-of-phase (MAX8537/max8538) or in-phase (max8539) operation ? 4.5v to 23v wide input range (operate down to 1.8v input with external 5v supply) ? tracking supply maintains v tt = v ttr = 1/2 v ddq ? adjustable output from 0.8v to 3.6v with 1% accuracy ? vttr reference sources and sinks up to 15ma ? 200khz to 1.4mhz adjustable switching frequency ? all-ceramic design achievable ? >90% efficiency ? independent pok_ and en_ ? adjustable soft-start and soft-stop for each output ? lossless adjustable-hiccup current limit ? output overvoltage protection ? 28-pin qsop package MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies ________________________________________________________________ maxim integrated products 1 19-3141; rev 0; 1/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information part temp range pin- package operation MAX8537 eei -40 c to +85 c 28 qsop out-of-phase tracking max8538 eei -40 c to +85 c 28 qsop out-of-phase nontracking max8539 eei -40 c to +85 c 28 qsop in-phase tracking pin configurations appear at end of data sheet.
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ..............................................................-0.3v to +25v avl, vl to gnd........................................................-0.3v to +6v pgnd to gnd .......................................................-0.3v to +0.3v fb_, en_, pok_ to gnd...........................................-0.3v to +6v refin, vttr, freq, ss_, comp_ to gnd....-0.3v to (avl + 0.3v) bst_, ilim_ to gnd ...............................................-0.3v to +30v dh1 to lx1 ...............................................-0.3v to (bst1 + 0.3v) dh2 to lx2 ...............................................-0.3v to (bst2 + 0.3v) lx_ to bst_ ..............................................................-6v to +0.3v lx_ to gnd................................................................-2v to +25v dl_ to pgnd ................................................-0.3v to (vl + 0.3v) continuous power dissipation (t a = +70?) 28-pin qsop (derate 10.8mw/? above +70?)........860mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) ..........................+300? electrical characteristics (v+ = 12v, en_ = vl, bst_ = 6v, lx_ = 1v, vl load = 0ma, c vl = 10? (ceramic), refin = 1.25v, pgnd = agnd = fb_ = ilim_ = 0v, c ss = 10nf, c vttr = 1?, r freq = 20k ? , dh_ = open, dl_ = open, pok_ = open, circuit of figure 1, t a = 0c to +85c, unless otherwise noted.) parameter conditions min typ max units general v+ operating range vl regulator drops out below 5.5v (note 1) 4.5 23.0 v v+/ vl operating range vl is externally generated (note 1) 4.5 5.5 v v+ operating supply current il(vl) = 0, fb_ forced 50mv above threshold 3.5 7 ma v+ standby supply current il(vl) = 0, bst_ = vl, en = lx_ = fb_ = 0v 350 700 ? vl regulator output voltage 5.5v < v+ < 23v, 1ma < i load < 70ma 4.75 5 5.25 v vl undervoltage-lockout trip level rising edge, hysteresis = 550mv (typ) (trip level is typically 85% of vl) 4.18 4.3 4.42 v output current this is for gate current of dl_ /dh_ drivers, c(vl) = 1?/10ma ceramic capacitor 70 ma thermal shutdown rising temperature, typical hysteresis = 10? +160 ? current-limit threshold (all current limits are tested at v+ = vl = 4.5v and 5.5v) ilim sink current ilim_ = lx - 200mv, 1.8v < lx < 23v, bst = lx +5v 180 200 220 ? soft-start soft-start source current ss_ = 100mv -7 -5 -3 ? soft-start sink current ss_ = 0.8 or refin 3 5 7 ? soft-start full-scale voltage 0.8 or refin v frequency low end of range r freq = 100k ? , v+ = vl = 5v 160 200 240 khz intermediate range r freq = 20k ? , v+ = vl = 5v 800 1000 1200 khz high end of range r freq = 14.3k ? , v+ = vl = 5v 1120 1400 1680 khz r freq = 100k ? 95 r freq = 20k ? 80 maximum duty cycle r freq = 14.3k ? 72 %
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = 12v, en_ = vl, bst_ = 6v, lx_ = 1v, vl load = 0ma, c vl = 10? (ceramic), refin = 1.25v, pgnd = agnd = fb_ = ilim_ = 0v, c ss = 10nf, c vttr = 1?, r freq = 20k ? , dh_ = open, dl_ = open, pok_ = open, circuit of figure 1, t a = 0c to +85c, unless otherwise noted.) parameter conditions min typ max units r freq = 100k ? 2.4 4 r freq = 20k ? 12 18 minimum duty cycle r freq = 14.3k ? 16 25 % dh_ minimum off-time 140 200 ns dh_ minimum on-time 120 ns error amplifier fb_ input bias current v fb _ = 0.8v 250 na fb1 input-voltage set point over line and load 0.792 0.800 0.808 v max8538 0.792 0.800 0.808 fb2 input-voltage set point MAX8537/max8539, refin = 0.9v 0.894 0.900 0.906 v op-amp open-loop voltage gain comp_ = 1.3v to 2.3v 72 >80 db op-amp gain bandwidth 25 mhz op-amp output-voltage slew rate 15 v/? drivers break-before-make time 30 ns dh1, dh2 on-resistance in low state 0.9 2.5 ? dh1, dh2 on-resistance in high state 1.3 2.5 ? dl1, dl2 on-resistance in low state 0.7 1.5 ? dl1, dl2 on-resistance in high state 1.6 2.8 ? logic inputs (en_) input low level 4.5v < vl < 5.5v 0.8 v input high level 4.5v < vl < 5.5v 2.4 v input bias current 0v to 5.5v -1 +0.1 +1 ? vttr vttr output voltage range source or sink 15ma 0.5 2.5 v vttr output accuracy -15ma i vttr +15ma, refin = 0.9v or 1.25v -1.0 refin +1.0 % refin refin input bias current refin = 0.9v or 1.25v -250 +250 na
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies 4 _______________________________________________________________________________________ electrical characteristics (continued) (v+ = 12v, en_ = vl, bst_ = 6v, lx_ = 1v, vl load = 0ma, c vl = 10? (ceramic), refin = 1.25v, pgnd = agnd = fb_ = ilim_ = 0v, c ss = 10nf, c vttr = 1?, r freq = 20k ? , dh_ = open, dl_ = open, pok_ = open, circuit of figure 1, t a = 0c to +85c, unless otherwise noted.) parameter conditions min typ max units refin input voltage range 0.5 2.5 v refin undervoltage-lockout trip level rising and falling edge, hysteresis = 15mv 0.4 0.45 0.5 v output-voltage fault comparators upper fb2 fault threshold rising voltage, hysteresis = 15mv 115 117 120 % of refin lower fb2 fault threshold falling voltage, hysteresis = 15mv 68 70 72 % of refin upper fb1 fault threshold rising voltage, hysteresis = 15mv 115 117 120 % of 0.8v lower fb1 fault threshold falling voltage, hysteresis = 15mv 68 70 72 % of 0.8v power-ok output (pok_) pok_ delay 64 clock cycles upper fb2 pok_ threshold rising voltage, hysteresis = 20mv 110 112 114 % of refin lower fb2 pok_ threshold falling voltage, hysteresis = 20mv 86 88 90 % of refin upper fb1 pok_ threshold rising voltage, hysteresis = 20mv 110 112 114 % of 0.8v lower fb1 pok_ threshold falling voltage, hysteresis = 20mv 86 88 90 % of 0.8v pok_ output low level i sink = 2ma 0.4 v pok_ output high leakage pok_ = 5.5v 1 a electrical characteristics (note 2) (v+ = 12v, en_ = vl, bst_ = 6v, lx_ = 1v, vl load = 0ma, c vl = 10? (ceramic), refin = 1.25v, pgnd = agnd = fb_ = ilim_ = 0v, c ss = 10nf, c vttr = 1?, r freq = 20k ? , dh_ = open, dl_ = open, pok_ = open, circuit of figure 1, t a = -40c to +85c, unless otherwise noted.) parameter conditions min typ max units v+ operating range vl regulator drops out below 5.5v (note 1) 4.75 23.00 v fb_ input-voltage set point over line and load 0.788 0.800 0.812 v fb2 input-voltage set point MAX8537/max8539, refin = 0.9v 0.891 0.900 0.909 v vttr output accuracy -15ma < i vttr +15ma, refin = 0.9v or 1.25v -1 refin +1 % note 1: operating supply range is guaranteed by the vl line-regulation test. user must short v+ to vl if a fixed 5v supply is used (i.e., if v+ is less than 5.5v). note 2: specifications to -40? are guaranteed by design, not production tested.
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies _______________________________________________________________________________________ 5 v ddq efficiency vs. load current MAX8537 toc01 load current (a) efficiency (%) 10 55 60 65 70 75 80 85 90 95 100 50 1 100 v ddq = 2.5v v ddq = 1.8v sense resistor = 0 ? v in = 12v v ddq efficiency vs. load current MAX8537 toc02 load current (a) efficiency (%) 10 55 60 65 70 75 80 85 90 95 100 50 1100 v ddq = 2.5v v ddq = 1.8v sense resistor = 3m ? v in = 12v v ddq vs. load current MAX8537 toc03 load current (a) v ddq 20 15 10 5 2.47 2.49 2.51 2.53 2.55 2.45 0 v in = 12v v tt vs. load current MAX8537 toc04 load current (a) v tt 12 9 6 3 1.21 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.29 1.30 1.20 015 v in = 12v v ttr vs. load current MAX8537 toc05 load current (ma) v ttr 20 15 10 5 1.21 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.29 1.30 1.20 025 v in = 12v output voltage vs. input voltage MAX8537 toc06 input voltage (v) output voltage (v) 13 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 1.2 12 14 v ddq v tt and v ttr i out _v ddq = 20a i out _v tt = 12a i out _v ttr = 15ma power-up MAX8537 toc07 v ddq 1v/div v ttr 8.5v/div v tt 8.5v/div v+ 5v/div 4ms/div power-down MAX8537 toc08 4ms/div 2v/div 2v/div 2v/div 5v/div v in v ddq v tt v vttr startup and shutdown MAX8537 toc09 v ddq 2v/div v ttr 1v/div v tt 1v/div en1/en2 5v/div 1ms/div t ypical operating characteristics (circuit of figure 1, t a = +25?, 400khz switching frequency, v in = 12v, unless otherwise noted.)
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies 6 _______________________________________________________________________________________ power-ok MAX8537 toc10 pok1 5v/div pok2 5v/div v tt 1v/div v ddq 2v/div 2ms/div i out _v ddq = 20a i out _v tt = 8a v tt startup and shutdown MAX8537 toc11 v tt 1v/div v ddq 2v/div v ttr 1v/div en2 5v/div 2ms/div v ddq load transient and v tt tracking MAX8537 toc12 v tt 50mv/div v ddq _i out 10a/div v ttr 50mv/div v ddq 100mv/div 200 s/div v tt _i out = 12a v ttr = 15ma di/dt = 5a/ s 20a 10a v tt load-transient response MAX8537 toc13 v ttr ac-coupled 50mv/div v tt _i out 10a/div v ddq ac-coupled 50mv/div v tt ac-coupled 50mv/div 200 s/div i out _v ddq = 20a i out _v ttr = 15ma di/dt = 1a/ s 8a -8a v ddq = 2.5v at 20a bode plot, v in = 12v MAX8537 toc14 khz db (degrees) 100k 10k 1k -20 0 20 40 60 80 100 120 140 160 180 -40 100 1m v tt = 1.25v at 12a bode plot, v in = 12v MAX8537 toc15 hz db (degrees) 10 5 10 4 10 3 -25 0 25 50 75 100 125 150 -50 10 2 10 6 short circuit and recovery MAX8537 toc16 10ms/div v out1 v out2 i l1 i in 1v/div 1v/div 10v/div 5a/div t ypical operating characteristics (continued) (circuit of figure 1, t a = +25?, 400khz switching frequency, v in = 12v, unless otherwise noted.)
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies _______________________________________________________________________________________ 7 pin description pin name (MAX8537/ max8539) name (max8538) function 1 bst2 bst2 bootstrap input to power internal high-side driver for step-down 2. connect to an external capacitor and diode according to figure 1. 2 dh2 dh2 high-side gate-driver output for step-down 2. swings from lx2 to bst2. 3 lx2 lx2 external inductor input for step-down 2. connect to the switched side of the inductor. lx2 serves as the lower supply-voltage rail for the dh2 high-side gate driver and the current-limit circuitry. 4 ilim2 ilim2 output current-limit setting for step-down 2. connect a resistor from ilim2 to the drain of the step-down 2 high-side mosfet, or to the junction of the source of the high-side mosfet and the current-sense resistor to set the current-limit threshold. see the current-limit setting section. 5 pok1 pok1 open-drain output. high impedance when step-down 1 is within 12% of its regulation voltage. pok1 is pulled low in shutdown. 6 dl2 dl2 low-side gate-driver output for step-down 2. swings from pgnd to vl. 7 pok2 pok2 open-drain output. high impedance when step-down 2 is within 12% of its regulation voltage. pok2 is pulled low in shutdown or if refin is undervoltage. 8 en2 en2 enable input for step-down 2 (also for vttr for the MAX8537 and max8539) 9 en1 en1 enable input for step-down 1 10 freq freq frequency adjust. connect a resistor from this pin to ground to set the frequency. the range of the freq resistor is 163k ? , 20k ? , and 100k ? (corresponding to 1.4mhz, 1.0mhz, and 200khz). 11 comp2 comp2 compensation pin for step-down 2. connect to compensation networks. 12 fb2 fb2 feedback input for step-down 2 with v refin as the threshold. user must have impedance <40k ? . 13 ss2 ss2 soft-start for step-down 2. connect a capacitor to gnd to set the soft-start time. refin reference input for v tt and v ttr . connect it to a resistor-divider from v ddq . refin common-mode voltage range is 0.5v to 2.5v. current through the divider-resistors must be 100?. 14 ? .c. for the max8538, connect pin 14 to gnd. 15 gnd gnd analog ground for internal circuitry 16 ss1 ss1 soft-start for step-down 1. connect a capacitor to gnd to set the soft-start time. 17 fb1 fb1 feedback input for step-down 1 with 0.8v threshold. user must have impedance <40k ? . 18 comp1 comp1 compensation pin for step-down 1. connect to compensation networks. vttr vttr output capable of sourcing and sinking up to 15ma. always bypass with a 1? ceramic capacitor (or larger) to gnd. 19 gnd analog ground for internal circuitry 20 avl avl analog vl input pin. connect to vl through a 4.7 ? resistor. bypass with a 0.1? (or larger) ceramic capacitor to gnd. 21 v+ v+ input supply voltage
MAX8537/max8538/max8539 detailed description the MAX8537/max8539 controllers provide a complete power-management solution for both ddr and combin- er supplies. the MAX8537 and max8539 are config- ured for out-of-phase and in-phase ddr power-supply operations, respectively. in addition to the dual-syn- chronous buck controllers, they also contain an addi- tional amplifier to generate a total of three outputs: the main memory voltage (v ddq ), the tracking sinking/sourcing termination voltage (v tt ), and the ter- mination reference voltage (v ttr ). the max8538 is configured as a dual out-of-phase controller for point- of-load supplies. each buck controller can source or sink up to 25a of current, while the termination refer- ence can supply up to 15ma output. the MAX8537/max8539 have a 1% accurate refer- ence. the first buck controller generates v ddq using external resistor-dividers. the second synchronous buck controller and the amplifier generate 1/2 v ddq voltage for v tt and v ttr . the v tt and v ttr voltages are maintained within 1% of 1/2 v ddq . the MAX8537/max8538/max8539 use a constant-fre- quency voltage-mode architecture with operating fre- quencies of 200khz to 1.4mhz to allow flexible design. an internal high-bandwidth (25mhz) operational ampli- fier is used as an error amplifier to regulate the output voltage. this allows fast transient response, reducing the number of output capacitors. synchronous rectifica- tion ensures high efficiency and balanced current sourcing and sinking capability for v tt . an all-n-fet design optimizes efficiency and cost. the two convert- ers can be operated in-phase or out-of-phase to mini- mize capacitance and optimize performance for all v in /v out combinations. both channels have independent enable and power- good functions. they also have high-side current-sense architectures. ilim pins allow the setting of an adjustable, lossless current limit for different combina- tions of load current and r ds(on) . additionally, accu- rate overcurrent protection is achieved by using a sensing resistor in series with the high-side fet. the positive current-limit threshold is programmable through an external resistor. overvoltage protection is achieved by latching off the high-side mosfet and latching on the low-side mosfet when the output volt- age exceeds 17% of its set output. dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies 8 _______________________________________________________________________________________ pin description (continued) pin name (MAX8537/ max8539) name (max8538) function 22 vl vl internal 5v linear regulator to power the ic. vl is always on. bypass with a ceramic capacitor with 1?/10ma of load current. the internal vl regulator can be disabled by connecting vl and v+ to an externally generated 5v. vl output current can be boosted with an external pnp transistor. 23 dl1 dl1 low-side gate-driver output for step-down 1. swings from pgnd to vl. 24 pgnd pgnd power ground for gate-driver circuits 25 ilim1 ilim1 output current-limit setting for step-down 1. connect a resistor from ilim1 to the drain of the step-down 1 high-side mosfet, or to the junction of the source of the high-side mosfet and the current-sense resistor to set the current-limit threshold. see the current-limit setting section. 26 lx1 lx1 external inductor input for step-down 1. connect to the switched side of the inductor. lx1 serves as the lower supply-voltage rail for the dh1 high-side gate driver and current-limit circuitry. 27 dh1 dh1 high-side gate-driver step-down 1. swings from lx1 to bst1. 28 bst1 bst1 bootstrap input to power internal high-side driver for step-down 1. connect to an external capacitor and diode according to figure 1.
dc-dc controller the MAX8537/max8538/max8539 step-down dc-dc converters use a pwm voltage-mode control scheme. an internal high-bandwidth (25mhz) operational amplifi- er is used as an error amplifier to regulate the output voltage. the output voltage is sensed and compared with an internal 0.8v reference or refin to generate an error signal. the error signal is then compared with a fixed-frequency ramp by a pwm comparator to give the appropriate duty cycle to maintain output voltage regula- tion. at the rising edge of the internal clock, and with dl (the low-side mosfet gate drive) at 0v, the high-side mosfet turns on. when the ramp voltage reaches the error-amplifier output voltage, the high-side mosfet latches off until the next clock pulse. during the high- side mosfet on-time, current flows from the input, through the inductor, and to the output capacitor and load. at the moment the high-side mosfet turns off, the energy stored in the inductor during the on-time is released to support the load as the inductor current ramps down by commutation through the low-side mosfet body diode. after a fixed delay, the low-side mosfet turns on to shunt the current from its body diode for lower voltage drop and increased efficiency. the low-side mosfet turns off at the rising edge of the next clock pulse, and when its gate voltage discharges to zero, the high-side mosfet turns on and another cycle starts. the controllers sense peak inductor current and pro- vide hiccup-mode overload and short-circuit protection (see the current limit section). the MAX8537/max8538/max8539 operate in forced- pwm mode where the inductor current is always contin- uous, so even under light load the controller maintains a constant switching frequency to minimize noise and possible interference with system circuitry. synchronous-rectifier driver (dl) synchronous rectification reduces the conduction loss in the rectifier by replacing the normal schottky catch diode with a low-resistance mosfet switch. the MAX8537/max8538/max8539 controllers also use the synchronous rectifier to ensure proper startup of the boost gate-drive circuit. high-side gate-drive supply (bst) gate-drive voltage for the high-side n-channel switch is generated by a flying-capacitor boost circuit (figure 1). the capacitor between bst and lx is alternately charged from the vl supply and placed in parallel to the high-side mosfet? gate-source terminals. on startup, the synchronous rectifier (low-side mosfet) forces lx to ground and charges the boost capacitor to vl. on the second half-cycle, the switch- mode power supply turns on the high-side mosfet by closing an internal switch between bst and dh. this provides the necessary gate-to-source voltage to turn on the high-side switch, an action that boosts the 5v gate-drive signal above the input voltage. internal 5v linear regulator all MAX8537/max8538/max8539 functions are pow- ered from the on-chip low-dropout 5v regulator with the input connected to v+. bypass the regulator? output (vl) with a 1?/10ma or greater ceramic capacitor. the v+ to vl dropout voltage is typically 500mv, so when v+ is less than 5.5v, vl is typically (v+ - 500mv). the internal linear regulator can source up to 70ma to supply the ic, power the low-side gate drivers, and charge the external boost capacitors. the current required to drive the external mosfets is calculated as the total gate charge of the mosfets at 5v multiplied by the switching frequency. at higher frequency, the mosfet drive current may exceed the capability of the internal linear regulator. the output current at vl can be supplemented with an external pnp transistor as shown in figures 4 and 5, which also moves most of the power dissipation off the ic. the external pnp can increase the output current at vl to over 200ma. the dropout voltage increases to 1v (typ). undervoltage lockout (uvlo) if vl drops below 3.75v, the MAX8537/max8538/ max8539 assume that the supply voltage is too low to make valid decisions, so uvlo circuitry inhibits switch- ing and forces pok and dh low and dl high. after vl rises above 4.3v, the controller powers up the outputs (see the startup section). startup externally, the MAX8537/max8538/max8539 start switching when vl rises above the 4.3v uvlo thresh- old. however, the controller does not start unless all four of the following conditions are met: 1) en_ is high, 2) vl > 4.3v, 3) the internal reference exceeds 80% of its nominal value (v ref > 0.64v), and 4) the thermal limit is not exceeded. once the MAX8537/max8538/ max8539 assert the internal enable signal, the con- troller starts switching and enables soft-start. MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies _______________________________________________________________________________________ 9
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies 10 ______________________________________________________________________________________ MAX8537 dl2 comp2 gnd pok2 en1 vttr fb2 ss2 fb1 ilim2 pgnd lx2 ilim1 freq avl v+ vl dl1 lx1 dh1 u1 bst1 bst2 dh2 en2 refin ss1 comp1 pok1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 c17 3.9nf c16 1 f vl vl vl c2 10 f c3 1000 f c28 1000 f c29 1000 f c5 0.47 f c8 47pf c6 0.47 f c9 47pf c11, c30, c31, c32 680 f c12, c36 220 f c13 10 f c14 1 f c15 1 f c19 8.2nf c18 15pf c20 39pf c21 3.9nf c22 820pf c24 0.01 f c25 220pf d1 d2 r2 402 ? r3 402 ? r19 100k ? r20 100k ? r5 100k ? r6 100k ? r7 2.2 ? r8 4.7 ? r9 51.1k ? r10 10.0k ? r11 51k ? r12 510 ? r13 1.2k ? r15 21.5k ? r17 10.0k ? r18 10.0k ? n1 n5 n8 n7 l1 0.9 h l2 0.8uh pok1 pok2 en1 en2 vin (10.8v to 13.2v) vout2 1.25v/ 12a vout1 2.5v/20a vttr r16 10.0k ? c23 0.01 f r14 22k ? c4 10 f n3 n4 c1 1000 f c26 1000 f c27 1000 f r1 0.005 ? r24 3.3 ? c41 47nf c42 0.15 f r4 0.003 ? r25 3.3 ? figure 1. typical application circuit: MAX8537 ddr memory application (400khz switching)
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies ______________________________________________________________________________________ 11 max8539 dl2 comp2 gnd pok2 en1 vttr fb2 ss2 fb1 ilim2 pgnd lx2 ilim1 freq avl v+ vl dl1 lx1 dh1 bst1 u1 bst2 dh2 en2 refin ss1 comp1 pok1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 c17 1.8nf c16 1 f vl vl vl c2 10 f vout1 c3 1000 f c28 1000 f c29 1000 f c5 0.47 f c6 0.47 f c11, c30, c31, c32 680uf c12, c36, c37 680 f c13 10 f c14 1 f c40 2.2nf c15 1 f c19 2.2nf c18 10pf c20 56pf c21 15nf c22 2.7nf c24 0.01 f c25 220pf d1 d2 r19 100k ? r20 100k ? r5 100k ? r6 100k ? r7 2.2 ? r8 4.7 ? r9 51.1k ? r10 10.0k ? r11 82k ? r12 2.2k ? r13 2.2k ? r15 12.7k ? r17 10.0k ? r18 10.0k ? n1 n5 n7 n8 l1 0.8 h l2 0.5uh c39 1.0nf pok1 pok2 en1 en2 vin (10.8v to 13.2v) vout2 0.9v/ 7a vout1 1.8v/15a vout1 vttr r16 10.0k ? c23 0.01 f r14 12k ? c4 10 f n4 n3 r21 2.2 ? r2 750 ? c7 0.1 f r22 1.5 ? r3 1.0k ? c10 0.1 f r25 1 ? r24 1 ? figure 2. max8539 ddr memory application (400khz switching)
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies 12 ______________________________________________________________________________________ max8538 dl2 comp2 gnd pok2 en1 gnd fb2 ss2 fb1 ilim2 pgnd lx2 ilim1 freq avl v+ vl dl1 lx1 dh1 bst1 bst2 dh2 en2 n.c. ss1 comp1 pok1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 c17 6.8nf vl vl vl c2 10 f c3 1000 f c28 1000 f c29 1000 f c5 0.47 f c6 0.47 f c12, c26 680 f c13 10 f c14 1 f c15 1 f c19 1.8nf c18 10pf c20 47pf c21 0.010 f c22 2.2nf c24 0.01 f c23 0.01 f d1 d2 r19 100k ? r20 100k ? r5 100k ? r6 100k ? r7 2.2 ? r8 4.7 ? r9 51.1k ? r10 21.5k ? r11 21.5k ? r12 1.0k ? r13 2.2k ? r15 12.7k ? n1 n5 n7 n8 l1 1.0 h l2 3.2 h c39 1.0nf pok1 pok2 en1 en2 vin (10.8v to 13.2v) vout2 2.5v/ 5a vout1 1.8v/15a r16 10.0k ? r14 14k ? n4 n3 r21 2.2 ? r2 511 ? c7 0.1 f r22 1.5 ? r3 1.0k ? c10 0.1 f c1 1000 f c11 470 f r23 10.0k ? c4 10 f c40 2.2nf u1 r24 1 ? r25 1 ? figure 3. max8538 powerpc application (400khz switching) powerpc is a trademark of motorola, inc.
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies ______________________________________________________________________________________ 13 max8538 dl2 comp2 gnd pok2 en1 gnd fb2 ss2 fb1 ilim2 pgnd lx2 ilim1 freq avl v+ vl dl1 lx1 dh1 bst1 bst2 dh2 en2 n.c. ss1 comp1 pok1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 n3 26 27 28 c17 3.9nf vl vl vl c2 10 f c3 1000 f 25v c28 1000 f 25v c29 1000 f 25v c5 0.47 f c6 0.47 f c12, c36 330 f c13 10 f c14 1 f c15 1 f c19 1nf c18 15pf c20 10pf c21 2.7nf c22 680pf c24 0.01 f d1 d2 r19 100k ? r20 100k ? r5 100k ? r6 100k ? r7 68 ? r8 4.7 ? r9 20.0k ? r10 21.5k ? r11 21.5k ? r12 4.3k ? r13 6.2k ? r15 31.6k ? n1 n5 n7 l1 0.66 h l2 0.66 h c39 2.2nf pok1 pok2 en1 en2 vin (10.8v to 13.2v) vout2 2.5v/ 10a vout1 3.3v/12a r16 10.0k ? r14 33k ? r21 1.5 ? r2 1.0k ? c7 0.1 f r3 1.21k ? r22 1.5 ? c10 0.1 f c1 1000 f 25v c26 1000 f 25v c11 330 f r23 10.0k ? c4 10 f u1 c30 330 f c40 2.2nf q1 c23 0.01 f r24 1 ? r25 1 ? figure 4. max8538 dual-output application (1mhz switching)
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies 14 ______________________________________________________________________________________ power-good signal (pok_) the power-good signal (pok_) is an open-drain output. the mosfet turns on and pok_ is held low until fb_ is ?2% from its nominal threshold (0.8v for fb1 and v refin for fb2). then there is a 64 clock-cycle delay before pok_ goes high impedance. for 400khz switch- ing frequency, this delay is 160?. to obtain a logic voltage output, connect a pullup resistor from pok_ to vl. a 100k ? resistor works well for most applications. if unused, leave pok_ grounded or unconnected. enable (en_), soft-start, and soft-stop outputs of the MAX8537/max8538/max8539 can be turned on with logic high and off with logic low inde- pendently at en1 and en2. en1 controls step-down 1, and en2 controls step-down 2 and vttr (MAX8537/ max8539 only). on the rising edge of en_, the controller enters soft- start. soft-start gradually ramps up the reference volt- age seen by the error amplifier to control the output? rate of rise and reduce the input surge current during startup. the soft-start period is determined by a 5a pullup current, the external soft-start capacitor connect- ed from ss_ to ground, and the reference voltage (0.8v for fb1 and v refin for fb2, on the MAX8537/max8539; 0.8v for fb2 on the max8538). the output reaches reg- ulation when soft-start is completed. on the falling edge of en_, the controller enters soft-stop, which reverses the soft-start ramp. however, there is a delay due to 1v overcharge on the soft-start capacitor. the delay time can be calculated as t delay = c ss x 1v / 5?. at the end of soft-stop, dh is low and dl is high. current limit the MAX8537/max8538/max8539 dc-dc step-down controllers sense the peak inductor current either through the on-resistance of the high-side mosfet for lossless sensing, or with a series resistor for more accurate sensing. in either case, when peak voltage across the sensing circuit (which occurs at the peak of the inductor current) exceeds the current-limit threshold set by the ilim pin, the controller turns off the high-side mosfet and turns on the low-side mosfet. the MAX8537/max8538/max8539 current-limit threshold can be set by an external resistor that works in con- junction with an internal 200? current sink. see the design procedure section for how to set the ilim with an external resistor. as the output load current increases above the thresh- old required to trip the peak current limit, the output voltage sags because the truncated duty cycle is insuf- ficient to support the load current. when fb_ is 30% below its nominal threshold, output undervoltage pro- tection is triggered and the controller enters hiccup mode to limit the power dissipation in a fault condition. see the output undervoltage protection (uvp) section for a description of hiccup operation. output undervoltage protection (uvp) output uvp begins when the controller is at its current limit, fb_ is 30% below its nominal threshold, and soft- start is complete. this condition causes the controller to drive dh and dl low, and to discharge the soft-start capacitor with a 5a pulldown current until v ss reaches 50mv. then the controller begins switching and enables soft-start. if the overload condition still exists when soft- start is complete, uvp triggers again. the result is hic- cup mode, where the controller attempts to restart periodically as long as the overload condition exists. in hiccup mode, the soft-start capacitor voltage ramps from the nominal fb_ threshold + 12% down to 50mv. for the MAX8537/max8539, the tracking step-down must also have v refin > 0.45v to trigger uvp. then the soft-start capacitor voltage ramps from v refin + 12% down to 50mv. additionally, in the MAX8537/max8539 if output 1 is shorted, output 2 latches off. recycle the input power or enable to restart output 2. output overvoltage protection (ovp) the output voltages are continuously monitored for overvoltage. if the output voltage is more than 17% above the reference of the error amplifier, ovp is trig- gered after a 10? delay and the controller turns off. the dl low-side gate driver is latched high until en_ is toggled or v+ power is cycled below 3.75v. this action turns on the synchronous-rectifier mosfet with 100% duty cycle and, in turn, rapidly discharges the output filter capacitor and forces the output to ground. note that dl latching high causes the output voltage to go slightly negative due to energy stored in the output lc at the instant ovp activates. if the load cannot toler- ate being forced to a negative voltage, it can be desir- able to place a power schottky diode across the output to act as a reverse-polarity clamp. for step-down 2 of the MAX8537/max8539, the ovp threshold is 560mv for v refin 0.45v, and the ovp threshold is v refin + 17% for v refin > 0.45v. thermal-overload protection thermal-overload protection limits total power dissipa- tion in the MAX8537/max8538/max8539. when the junction temperature exceeds t j = +160?, a thermal sensor shuts down the device, forcing dh and dl low and allowing the ic to cool. the thermal sensor turns the part on again after the junction temperature cools
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies ______________________________________________________________________________________ 15 by 10?, resulting in a pulsed output during continuous thermal-overload conditions. during a thermal event, the switching converters are turned off, pok1 and pok2 are pulled low, and the soft-starts are reset. design procedure output voltage setting the output voltage can be set by a resistive divider net- work. select r2, the resistor from fb to gnd, between 5k ? and 15k ? . then calculate r1 by: r1 = r2 x [(v out / 0.8) -1] inductor selection there are several parameters that must be examined when determining which inductor to use: input voltage, output voltage, load current, switching frequency, and lir. lir is the ratio of inductor current ripple to dc load current. a higher lir value allows for a smaller induc- tor, but results in higher losses and higher output rip- ple. a good compromise between size and efficiency is a 30% lir. once all the parameters are chosen, the inductor value is determined as follows: where f s is the switching frequency. choose a standard value close to the calculated value. the exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, and efficiency. lower inductor values minimize size and cost, but also increase the output ripple and reduce the efficiency due to higher peak currents. on the other hand, higher inductor values increase efficiency, but eventually resistive losses due to extra turns of wire exceed the benefit gained from lower ac current levels. find a low- loss inductor with the lowest possible dc resistance that fits the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well up to 300khz. the chosen inductor? saturation current rating must exceed the peak inductor current determined as: input capacitor the input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit? switching. the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents defined by the following equation: combinations of large electrolytic and small ceramic capacitors in parallel are recommended. almost all of the rms current is supplied from the large electrolytic capacitor, while the smaller ceramic capacitor supplies the fast rise and fall switching edges. choose the elec- trolytic capacitor that exhibits less than 10 c tempera- ture rise at the maximum operating rms current for optimum long-term reliability. output capacitor the key selection parameters for the output capacitor are the actual capacitance value, the equivalent series resistance (esr), the equivalent series inductance (esl), and the voltage-rating requirements, which affect the overall stability, output ripple voltage, and transient response. the output ripple has three components: variations in the charge stored in the output capacitor, voltage drop across the capacitor? esr, and voltage drop across the capacitor? esl, caused by the current into and out of the capacitor. the following equations estimate the worst-case ripple: where i p-p is the peak-to-peak inductor current (see the inductor selection section). higher output current requires paralleling multiple capacitors to meet the out- put ripple voltage. the MAX8537/max8538/max8539s?response to a load transient depends on the selected output capacitor. after a load transient, the output instantly changes by (esr x ? i load )+ (esl x di/dt). before the controller can respond, the output deviates further depending on the inductor and output capacitor values. after a short period of time (see the typical operating characteris- tics ), the controller responds by regulating the output voltage back to its nominal state. the controller response time depends on the closed-loop bandwidth. with higher bandwidth, the response time is faster, pre- vv v v vi esr vicf vv esl l esl i vv fl v v ripple ripple esr ripple c ripple esl ripple esr p p ripple c p p out sw ripple esl in pp in out sw out in =++ = = = + = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? / ( ) / ( ) () () () () () () 8 i ivvv ivvv v rms out out in out out out in out in = ? + ? [()] [()] 11 12 2 2 22 ii lir i peak load max load max =+ ? ? ? ? ? ? () () 2 l vvv vfi lir out in out in s load max = ? ( ) ()
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies 16 ______________________________________________________________________________________ venting the output capacitor voltage from further devia- tion from its regulating value. do not exceed the capacitor? voltage or ripple current ratings. mosfet selection the MAX8537/max8538/max8539 controllers drive two external, logic-level, n-channel mosfets as the circuit- switch elements. the key selection parameters are: 1) on-resistance (r ds(on) ): the lower, the better. 2) maximum drain-to-source voltage (v dss ): should be at least 20% higher than the input supply rail at the high-side mosfet? drain. 3) gate charges (q g , q gd , q gs ): the lower, the better. choose mosfets with r ds(on) rated at v gs = 4.5v. for a good compromise between efficiency and cost, choose the high-side mosfet that has conduction loss equal to the switching loss at the nominal input voltage and maximum output current. for the low-side mosfet, make sure it does not spuriously turn on due to dv/dt caused by the high-side mosfet turning on, as this results in shoot-through current degrading the efficiency. mosfets with a lower q gd /q gs ratio have higher immu- nity to dv/dt. for proper thermal-management design, the power dis- sipation must be calculated at the desired maximum operating junction temperature, maximum output cur- rent, and worst-case input voltage (for low-side mosfet, worst case is at v in(max) ; for high-side mosfet, it could be either at v in(min) or v in(max) ). high-side and low-side mosfets have different loss components due to the circuit operation. the low-side mosfet, operates as a zero-voltage switch; therefore, the major losses are the channel conduction loss (p lscc ) and the body-diode conduction loss (p lsdc ): p lscc = [1 - (v out / v in )] x (i load ) 2 x r ds,on use r ds,on at t j(max) : p lsdc = 2 x i load x v f x t dt x f s where v f is the body-diode forward voltage drop, t dt is the dead-time between the high-side mosfet and the low-side mosfet switching transitions, and f s is the switching frequency. the high-side mosfet operates as a duty-cycle control switch and has the following major losses: the channel conduction loss (p hscc ), the v i overlapping switching loss (p hssw ), and the drive loss (p hsdr ). the high-side mosfet does not have body-diode conduction loss because the diode never conducts current. p hscc = (v out / v in ) x i 2 load x r ds(on) use r ds(on) at t j(max): p hssw = v in x i load x f s x [(q gs + q gd ) / i gate ] where i gate is the average dh-high driver output- current capability determined by: i gate(on) = 2.5 / (r dh + r gate ) where r dh is the high-side mosfet driver? average on-resistance (1.1 ? typ) and r gate is the internal gate resistance of the mosfet (~2 ? ): p hsdr = q gs x v gs x f s x r gate / (r gate + r dh ) where v gs ~ vl = 5v . in addition to the losses above, approximately 20% more for additional losses due to mosfet output capaci- tances and low-side mosfet body-diode reverse-recov- ery charge dissipated in the high-side mosfet that exists, but is not well defined in the mosfet data sheet. refer to the mosfet data sheet for thermal-resistance specification to calculate the pc board area needed to maintain the desired maximum operating junction tem- perature with the above-calculated power dissipation. to reduce emi caused by switching noise, add a 0.1? ceramic capacitor from the high-side switch drain to the low-side switch source or add resistors in series with dh and dl to slow down the switching transitions. however, adding series resistors increases the power dissipation of the mosfets, so be sure this does not overheat the mosfets. the minimum load current must exceed the high-side mosfet? maximum leakage current over temperature if fault conditions are expected. current-limit setting the MAX8537/max8538/max8539 controllers sense the peak inductor current to provide constant current and hiccup current limit. the peak current-limit thresh- old is set by an external resistor together with the inter- nal current sink of 200?. the voltage drop across the resistor r ilim_ with 200? current through it sets the maximum peak inductor current that can flow through the high-side mosfet or the optional current-sense resistor by the equations below: i peak(max) = 200? x r ilim_ / r dson(hsfet) or i peak(max) = 200? x r ilim_ / r sense r ilim_ should be less than 1.5k ? for optimum current- limit accuracy. the actual corresponding maximum load current is lower than the i peak(max) above by half
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies ______________________________________________________________________________________ 17 of the inductor ripple current (see the inductor selection section). if r ds(on) of the high-side mosfet is used for current sensing, make sure to use the maxi- mum r ds(on) at the highest operating junction temper- ature to avoid fault tripping of the current limit at elevated temperature. consideration should also be given to the tolerance of the 200? current sink. when r ds(on) of the high-side mosfet is used for cur- rent sensing, ringing on the lx voltage waveform can interfere with the current limit. below is the procedure for selecting the value of the series rc snubber circuit: 1) connect a scope probe to measure v lx to gnd, and observe the ringing frequency, f r . 2) find the capacitor value (connected from lx to gnd) that reduces the ringing frequency by half. the circuit parasitic capacitance (c par ) at lx is then equal to 1/3rd the value of the added capaci- tance above. the circuit parasitic inductance (l par ) is calculated by: the resistor for critical dampening (r snub ) is equal to 2 x f r x l par . adjust the resistor value up or down to tailor the desired damping and the peak voltage excursion. the capacitor (c snub ) should be at least 2 to 4 times the value of the c par in order to be effective. the power loss of the snubber circuit is dissipated in the resistor (p rsnub ) and can be calculated as: where v in is the input voltage and f sw is the switching frequency. choose an r snub power rating that meets the specific application? derating rule for the power dissipation calculated. additionally, there is parasitic inductance of the cur- rent-sensing element, whether the high-side mosfet r ds(on) (l sense_fet ) or the actual current-sense resistor r sense (l rsense ) are used, which is in series with the output filter inductor. this parasitic inductance, together with the output inductor, form an inductive divider and cause error in the current-sensing voltage. to compensate for this error, a series rc circuit can be added in parallel with the sensing element (see figure 1). the rc time constant should equal l rsense / r sense , or l sense_fet / r ds(on) . first, set the value of r equal to or less than r ilim_ / 100. then, the value of c can be calculated as: c = l rsense / (r sense x r) or c = l sense_fet / (r ds(on) x r) any pc board trace inductance in series with the sens- ing element and output inductor should be added to the specified fet or resistor inductance per the respective manufacturer? data sheet. for the case of the mosfet, it is the inductance from the drain to the source lead. an additional switching noise filter may be needed at ilim_ by connecting a capacitor in parallel with r ilim_ (in the case of r ds(on) sensing) or from ilim_ to lx (in the case of resistor sensing). for the case of r ds(on) sensing, the value of the capacitor should be: c > 50 / (3.1412 x f s x r ilim_ ) for the case of resistor sensing: c < 25 x 10 -9 / r ilim_ soft-start capacitor setting the two step-down converters have independent, adjustable soft-start. external capacitors from ss1/ss2 to ground are charged by an internal 5a current source to the corresponding feedback threshold. therefore, the soft-start time can be calculated as: t ss = c ss x v fb / 5? for example, 0.01? from ss1 to ground corresponds to approximately a 1.6ms soft-start period for step- down 1. compensation design the MAX8537/max8538/max8539 use a voltage-mode control scheme that regulates the output voltage by comparing the error-amplifier output (comp) with a fixed internal ramp to produce the required duty cycle. the error amplifier is an operational amplifier with 25mhz bandwidth to provide fast response. the output lowpass lc filter creates a double pole at the resonant frequency that introduces a gain drop of 40db per decade and a phase shift of 180 degrees per decade. the error amplifier must compensate for this gain drop and phase shift to achieve a stable high-bandwidth closed-loop system. the basic regulator loop can be thought of as consist- ing of a power modulator and an error amplifier. the power modulator has dc gain set by v in / v ramp , with a double pole, f p_lc , and a single zero, f z_esr , set by the output inductor (l), the output capacitor (c o ), and its equivalent series resistance (r esr ). below are the equations that define the power modulator: pcvf rsnub snub in sw = () 2 l fc par r par = () 1 2 2
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies 18 ______________________________________________________________________________________ when the output capacitor is composed of paralleling n number of the same capacitors, then: thus, the resulting f z_esr is the same as that of a sin- gle capacitor. the total closed-loop gain must be equal to unity at the crossover frequency, where the crossover frequency is less than or equal to 1/5th the switching frequency (f s ): f c f s / 5 so the loop-gain equation at the crossover frequency is: g ea(fc) x g mod(fc) = 1 where g ea(fc) is the error-amplifier gain at f c , and g mod(fc) is the power-modulator gain at f c . the loop compensation is affected by the choice of out- put filter capacitor due to the position of its esr-zero fre- quency with respect to the desired closed-loop crossover frequency. ceramic capacitors are used for higher switching frequencies (above 750khz) and have low capacitance and low esr; therefore, the esr-zero fre- quency is higher than the closed-loop crossover frequen- cy. electrolytic capacitors (e.g., tantalum, solid polymer, and os-con) are needed for lower switching frequen- cies and have high capacitance and higher esr; there- fore, the esr-zero frequency is lower than the closed-loop crossover frequency. thus, the compensa- tion design procedures are separated into two cases: case 1: crossover frequency is less than the output- capacitor esr-zero (f c < f z_esr ). the modulator gain at f c is: g mod(fc) = g mod(dc) x (f p_lc / f c ) 2 since the crossover frequency is lower than the output capacitor esr-zero frequency and higher than the lc double-pole frequency, the error-amplifier gain must have a +1 slope at f c so that, together with the -2 slope of the lc double pole, the loop crosses over at the desired -1 slope. the error amplifier has a dominant pole at a very low frequency (~0hz), and two additional zeros and two additional poles as indicated by the equations below and illustrated in figure 6: f z1_ea = 1 / (2 x r4 x c2) f z2_ea = 1 / (2 x (r1 + r3) x c1) f p2_ea = 1 / (2 x r3 x c1) f p3_ea = 1 / (2 x r4 x (c2 x c3 / (c2 + c3))) note that f z2_ea and f p2_ea are chosen to have the converter closed-loop crossover frequency, f c , occur when the error-amplifier gain has +1 slope, between f z2_ea and f p2_ea . the error-amplifier gain at f c must meet the requirement below: g ea(fc) = 1 / g mod(fc) the gain of the error amplifier between f z1_ea and f z2_ea is: g ea (f z1_ea - f z2_ea ) = g ea(fc) x f z2_ea / f c = f z2_ea / (f c x g mod(fc) ) this gain is set by the ratio of r4/r1, where r1 is calcu- lated in the output voltage setting section. thus: r4 = r1 x f z2_ea / (f c x g mod(fc) ) where f z2_ea = f p_lc . due to the underdamped (q > 1) nature of the output lc double pole, the first error-amplifier zero frequency must be set less than the lc double-pole frequency in order to provide adequate phase boost. set the error- amplifier first zero, f z1_ea , at 1/4th the lc double-pole frequency. hence: c2 = 2 / ( x r4 x f p_lc ) set the error amplifier f p2_ea at f z_esr and f p3_ea equal to half the switching frequency. the error-amplifier gain between f p2_ea and f p3_ea is set by the ratio of r4/r i and is equal to: g ea (f z1_ea - f z2_ea ) x (f z_esr / f p_lc ) where r i = r1 x r3 / (r1 + r3). then: r i = r4 x f p_lc / (g ea (f z1_ea - f z2_ea ) x f z_esr ) = r4 x f c x g mod(fc) / f z_esr the value of r3 can then be calculated as: r3 = r1 x r i / (r1 ?r i ) now we can calculate the value of c1 as: c1 = 1 / (2 x r3 x f z_esr ) and c3 as: c3 = c2 / ((2 x c2 x r4 x f p3_ea ) - 1) cnc and r r n o each esr esr each = = _ g v v where v v typ f lc f rc mod dc in ramp ramp plc o z esr esr o () _ _ ,() == = = 1 1 2 1 2
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies ______________________________________________________________________________________ 19 gain (db) 0 f z1 f z2 f c f p2 f p3 frequency ea gain closed-loop gain figure 7. closed-loop and error-amplifier gain plot for case 2 c1 r3 r1 r2 v out fb ref ea comp c2 c3 r4 gain (db) 0 f z1 f z2 f c f p2 f p3 frequency ea gain closed-loop gain figure 6. error-amplifier compensation circuit; closed-loop and error-amplifier gain plot for case 1
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies 20 ______________________________________________________________________________________ freq osc en1 en2 comp1 avl refin ss2 gnd comp2 ilim1 bst1 dh1 lx1 dl1 pgnd v+ vl ss1 fb1 pok1 vttr ilim2 bst2 dh2 lx2 vl dl2 pgnd pok2 fb2 ovp2 uvp2 200 a uvp1 ovp1 imax sense pwm eamp soft-start soft-start eamp imax sense pwm eamp control logic 0.936v 0.80v 0.560v 0.896v 1v 0.704v control logic bias ref 0.7refin 1.17refin 1.12refin 0.88refin refin refin vl vl 200 a MAX8537/max8539 functional diagram
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies ______________________________________________________________________________________ 21 case 2: crossover frequency is greater than the output-capacitor esr zero (f c > f z_esr ) . the modulator gain at f c is: g mod(fc) = g mod(dc) x (f p_lc ) 2 / (f z_esr x f c ) since the output-capacitor esr-zero frequency is high- er than the lc double-pole frequency but lower than the closed-loop crossover frequency, where the modu- lator already has -1 slope, the error-amplifier gain must have zero slope at f c so the loop crosses over at the desired -1 slope. the error-amplifier circuit configuration is the same as case 1 above; however, the closed-loop crossover fre- quency is now between f p2 and f p3 as illustrated in figure 7. the equations that define the error amplifier? zeros (f z1_ea , f z2_ea ) and poles (f p2_ea , f p3_ea ) are the same as case 1; however, f p2_ea is now lower than the closed-loop crossover frequency. therefore, the error- amplifier gain between f z1_ea and f z2_ea is now calcu- lated as: g ea (f z1_ea - f z2_ea ) = g ea(fc) x f z2_ea / f p2_ea = f z2_ea / (f p2_ea x g mod(fc) ) this gain is set by the ratio of r4/r1, where r1 is calcu- lated in the output voltage setting section. thus: r4 = r1 x f z2_ea / (f p2_ea x g mod(fc) ) where f z2_ea = f p_lc and f p2_ea = f z_esr . similar to case 1, c2 can be calculated as: c2 = 2 / ( x r4 x f p_lc ) set the error-amplifier third pole, f p3_ea , at half the switching frequency, and let r i = (r1 x r3) / (r1 + r3). the gain of the error amplifier between f p2_ea and f p3_ea is set by the ratio of r4/r i and is equal to g ea(fc) = 1 / g mod(fc) . then: r i = r4 x g mod(fc) similar to case 1, r3, c1, and c3 can be calculated as: r3 = r1 x ri / (r1 - r i ) c1 = 1 / (2 x r3 x f z_esr ) c3 = c2 / ((2 x c2 x r4 x f p3_ea ) - 1) applications information pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching-power stage requires particular attention. follow these guidelines for good pc board layout: 1) place the decoupling capacitors as close to the ic pins as possible. refin ss2 fb2 comp2 freq en1 en2 pok2 dl2 pok1 ilim2 lx2 dh2 bst2 top view 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 bst1 dh1 lx1 ilim1 pgnd dl1 gnd vl v+ avl vttr comp1 fb1 ss1 qsop MAX8537 max8539 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 bst1 dh1 lx1 ilim1 pgnd dl1 gnd vl v+ avl gnd comp1 fb1 ss1 n.c. ss2 fb2 comp2 freq en1 en2 pok2 dl2 pok1 ilim2 lx2 dh2 bst2 qsop max8538 pin configurations
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies 22 ______________________________________________________________________________________ 2) keep separate the power ground plane (connected to the sources of the low-side mosfets, pin 24, input capacitor ground, output capacitor ground, and vl decoupling capacitor ground) and the signal ground plane (connected to gnd pin and the rest of the circuit ground returns). place the input decou- pling ceramic capacitor as directly and close to the high-side mosfet drain and the low-side mosfet source as possible. place the rc snubber circuit as close to the low-side mosfet as possible. 3) keep the high-current paths as short as possible. 4) connect the drains of the mosfets to a large land area to help cool the devices and further improve efficiency and long-term reliability. 5) ensure all feedback connections are short and direct. place the feedback resistors as close to the ic as possible. 6) route high-speed switching nodes away from sensi- tive analog areas (fb, comp). 7) refer to the evaluation kit for a sample board layout. chip information transistor count: 5504 process: bicmos
MAX8537/max8538/max8539 dual-synchronous buck controllers for point-of- load, tracking, and ddr memory power supplies maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 23 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qsop.eps e 1 1 21-0055 package outline, qsop .150", .025" lead pitch

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